LAUGHTON ELECTRONICS |
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One-bit Computing at 60 Hertz |
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This
page describes a tiny computer made from an EPROM and a few logic
chips. Although its specifications are ridiculously modest, the machine
readily satisfied application requirements.
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This
is a design I came up with in response to a customer's request to add
some new automated functions to a printing press. The new behavior
might reasonably have been achieved using hardwired gates, counters and
flip-flops, but I wanted to use programmable logic instead. (Later,
when additional presses were modified, I switched to using a
microcontroller.)
It was the Motorola MC14500 that introduced me to the idea of one-bit computing. The one-bit concept intrigued me, and eventually some pencil & paper designs revealed that, for lowest chip count, the 14500 itself could be omitted. Its tiny complement of 16 instructions was actually overkill for some jobs. In contrast to the 14500's 4-bit op-code, my design uses no op-code at all. That's because there's only one instruction and it executes endlessly. That instruction performs two functions: an Input Test, whose result controls a two-way branch; and an Output operation that writes 1 or 0 to any of the bits in the output register (a 4099 addressable latch). For the printing press application, the inputs were driven by mechanical switches and by a pair of logic signals from the original press wiring. The outputs drove Solid State Relays which, in turn, activated solenoids.The usual concept of a Program Counter does not apply; nor does the familiar conditional branch idiom of "branch, else fall through to the instruction at address+1." As noted, every instruction includes a two-way branch, meaning that address+1 is no different from any other branch destination. For the sake of human readability, instructions in the EPROM may be arranged in sequential order. But, even then, the machine operates by jumping from one instruction to the next, not counting (computing an increment). |
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Operation is based on an unvarying, two-phase cycle. Each phase fetches a byte from the EPROM.
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There's a wrinkle, and it's that each of the 256 destinations is organized to hold four bytes, not two. This is evident on the schematic. Notice that A1 of the EPROM is driven by Phase Two, and A0 is driven by the so-called Flag Bit (which contains the result of the Input Test that occurs on every instruction). When the Flag Bit is true, "true" instruction bytes will be fetched (ie; with EPROM A0 =1). When the Flag Bit is false, EPROM A0 will =0 and "false" instruction bytes will be fetched. That is the basis of the two-way branch mentioned earlier. The Input Test during Phase One selects one of the eight inputs to the 4051 mux, and that input's value is clocked into the Flag Bit at the start of Phase Two. During Phase Two, the Jump Destination is fetched, and the fetch will occur either with EPROM A0 =1 or =0, depending on the state of the 4051 input that was tested. Thus two different jump destinations can result. I mentioned that every instruction includes both an Input Test (for the two-way branch) and an Output operation. This can be inconvenient, because as you write a program, line by line, you'll usually want either an Input/branch or an Output to occur — not both. Luckily, it's an easy matter to neutralize one part or the other. An unwanted Input/branch operation is neutralized simply by making both branch destinations the same. It doesn't matter which input you specify for testing, since the result of the test is essentially ignored. Only the Output portion of the instruction will have any meaningful effect. As for neutralizing an Output operation, one bit (Q7) of the 4099 addressable latch is left unconnected for this exact purpose. It is reserved as a Write-Only-Memory! In other words, when you want the Output operation to be a NOP, code it to write to Q7. It doesn't matter whether you write a 1 or a 0. Q7 goes nowhere, leaving only the Input/branch portion of the instruction with any meaningful effect. This computer has no RAM as such, making it awkward if you need to store a bit of information. One approach is to simply branch the program into two paths, based on the status of the bit you need to remember. But, for long-term storage, a better approach is to write the bit to one of the dedicated 4099 outputs which connect back to 4051 inputs. This allows the stored information to be read back when needed. (The schematic shows two such I/O-mapped memory bits.) In the printing press application, there are a few subroutines that are called from two different sections of code. At the exit of each subroutine, a memory bit (previously prepared by the caller) is tested to see which of two return addresses to jump to. Also notable on the schematic are an RC filter to de-glitch the input line, and a Reset circuit that forces the EPROM to select a shadow array filled entirely with unconditional "Jump to Start" instructions. The clock oscillator can easily be replaced by a square wave derived from the AC power line. Of course this computer is capable of running a lot faster than 60 Hz, but 60 Hz is plenty fast enough for this application. I chose the low operating frequency merely because it simplified implementation of a software time delay. Two sections are unused on the lower 74C374 register. This means a 74C174 could replace the '374, reducing space requirements. Alternatively, one of the 374's unused sections could capture the unused bit from the EPROM, providing an extra address line to double the machine's Input or Output space via an additional 4051 or 4099. |
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