| Pointer Load Instructions |
Op-Code
(hex) |
Bytes
/Cycles |
Substituted
op-code |
Operation |
Address Mode |
Mnemonic |
Notes |
| 42 |
2 / 2 |
- |
Load DP0 |
Immediate |
LDDP0# |
|
| 54 |
2 / 4 |
- |
Load DP0 |
Zero-page,X |
LDDP0ZPG,X |
|
| DC |
3 / 4 |
- |
Load DP0 |
Absolute |
LDDP0ABS |
|
| C2 |
2 / 2 |
- |
Load DP1 |
Immediate |
LDDP1# |
|
| 44 |
2 / 3 |
- |
Load DP1 |
Zero-page |
LDDP1ZPG |
|
| D4 |
2 / 4 |
- |
Load DP1 |
Zero-page,X |
LDDP1ZPG,X |
|
| 0B |
3 / 4 |
DC |
Load DP1 |
Absolute |
LDDP1ABS |
|
| E2 |
2 / 2 |
- |
Load NCP |
Immediate |
LDNCP# |
|
| F4 |
2 / 4 |
- |
Load NCP |
Zero-page,X |
LDNCPZPG,X |
|
| FC |
3 / 4 |
- |
Load NCP |
Absolute |
LDNCPABS |
|
| Prefix Instructions |
Op-Code
(hex) |
Bytes
/Cycles |
Substituted
op-code |
Operation |
Address
Mode |
Mnemonic |
Notes |
| 83 |
1 / 1 |
03 |
DP0 prefix |
Implied |
DP0_PFX |
|
| C3 |
1 / 1 |
03 |
DP1 prefix |
Implied |
DP1_PFX |
|
| 43 |
1 / 1 |
03 |
NCP prefix |
Implied |
NCP_PFX |
|
| "2 in1" Instructions (standard
op with implicit prefix) |
Op-Code
(hex) |
Bytes
/Cycles |
Substituted
op-code |
Operation |
Address Mode |
Mnemonic |
Notes |
| F3 |
2 / 6 |
A1 |
Far LDA using DP1 |
(X,ind) |
LDAX):DP1 |
|
| E3 |
2 / 5 |
B1 |
Far LDA using DP1 |
(ind),Y |
LDA)Y:DP1 |
|
| D3 |
3 / 4 |
AD |
Far LDA using DP1 |
Absolute |
LDAABS:DP1 |
|
| B3 |
2 / 6 |
81 |
Far STA using DP0 |
(X,ind) |
STAX):DP0 |
|
| A3 |
2 / 6 |
91 |
Far STA using DP0 |
(ind),Y |
STA)Y:DP1 |
|
| 93 |
3 / 4 |
8D |
Far STA using DP0 |
Absolute |
STAABS:DP0 |
|
| 8B |
3 / 6 |
0C |
Far TSB using DP0 |
Absolute |
TSBABS:DP0 |
|
| 9B |
3 / 6 |
1C |
Far TRB using DP0 |
Absolute |
TRBABS:DP0 |
|
| Jump and Return
Instructions |
Op-Code
(hex) |
Bytes
/Cycles |
Substituted
op-code |
Operation |
Address Mode |
Mnemonic |
Notes |
| 13 |
3 / 3 |
4C |
Far JMP using NCP |
Absolute |
JMP:NCPX |
1 |
| 23 |
3 / 6 |
20 |
Far JSR using NCP |
Absolute |
JSR:NCPX |
1 |
| EB |
1 / 6 |
60 |
Far RTS using NCP |
Stack |
RTS:NCPX |
1 |
| FB |
1 / 6 |
40 |
Far RTI using NCP |
Stack |
RTI:NCPX |
2 |
| Push and Pull Instructions |
Op-Code
(hex) |
Bytes
/Cycles |
Substituted
op-code |
Operation |
Address Mode |
Mnemonic |
Notes |
| 6B |
1 / 3 |
08 |
Push DP0 |
Stack |
PHDP0 |
|
| 7B |
1 / 3 |
08 |
Push DP1 |
Stack |
PHDP1 |
|
| 4B |
1 / 3 |
08 |
Push CCP |
Stack |
PHCCP |
|
| 5B |
1 / 3 |
08 |
Push NCP |
Stack |
PHNCP |
|
| 63 |
1 / 4 |
7A |
Pull Y, copying
the value to DP0 |
Stack |
PLY=DP0 |
3 |
| 73 |
1 / 4 |
7A |
Pull Y, copying
the value to DP1 |
Stack |
PLY=DP1 |
3 |
| 53 |
1 / 4 |
7A |
Pull Y, copying
the value to NCP |
Stack |
PLY=NCP |
3 |
| 1B |
1 / 4 |
7A |
Pull Y, copying
value to IP lowbyte |
Stack |
PLY=IPL |
3 |
| 2B |
1 / 4 |
7A |
Pull Y, copying
value to IP highbyte |
Stack |
PLY=IPH |
3 |
| Miscellaneous Instructions |
Op-Code
(hex) |
Bytes
/Cycles |
Substituted
op-code |
Operation |
Address Mode |
Mnemonic |
Notes |
| AB |
3 / 6 |
0C |
Far TSB using DP0 |
( IP ) |
TSBIP):DP0 |
4 |
| BB |
3 / 6 |
1C |
Far TRB using DP0 |
( IP ) |
TRBIP):DP0 |
4 |
| 3B |
1 / 9 |
4C |
"Next." Jump (( IP
)) and
post-increment IP by 2 |
(( IP++ )) |
NEXT |
5 |
| 33 |
3 / * |
20 |
Far Scan using
NCP. (Reads bytes
for video horizontal scan line.) |
Absolute |
SCAN:NCP |
6
|
| DB |
2 / 6 |
81 |
STA and copy
pointer to W |
(X,ind) |
STAX)PTR>W |
8 |
| CB |
2 / 6 |
A1 |
LDA and copy
pointer to W |
(X,ind) |
LDAX)PTR>W |
8 |
| 03 |
2 / 2 |
03 |
One-cycle NOP |
Implied |
1CYNOP |
9 |
| 5C |
3 / 8 |
- |
Exchange CCP and
NCP |
Implied |
N<>C |
10 |
| 02 |
2 / 2 |
- |
Single increment
of IP |
Implied |
SINC |
7 |
| 22 |
2 / 2 |
- |
Double increment
of IP |
Implied |
DINC |
7 |
Notes:
- many of the mnemonics are lengthy because they also specify the
address mode (thus simplifying the mods to my assembler)
Note 1:
NCP is
eXchanged with CCP. "X" in the mnemonic denotes
this.
Note 2:
RTI:NCPX
is only useful as a form of jump, for a Debugger perhaps. The KK
typically did not use hardware interrupts because certain KK
instructions
can crash if interrupted. Circuitry to remedy this remains incomplete.
Note 3:
"Pull"
instructions cannot be created using NOPs. To increment the Stack
Pointer
a PLA, PLX, PLY or PLP is required and a register will be written to.
KK maps its pulls to the PLY opcode. The mnemonics remind the
programmer of this
compromise solution.
Note 4:
I think
I intended these for manipulation of pixel bit-maps,
with IP providing accelerated addressing through the array.
I don't recall whether the capability ever got used.
Note 5:
NEXT is
discussed on this
page
Note 6:
The Scan
instruction is discussed here.
Note 7:
SINC and
DINC are discussed here.
Note 8:
these
instructions are used to provide X-Indirect-Y Addressing,
explained here.
Note 9:
1CYNOP
(1-cycle NOP) is intended for software timing loops
Note 10:
N<>C is used during initialization, before the 16MB
map is enabled, as a means to load CCP. Otherwise it is suicidal to
load
CCP but not the PC.
|
