LAUGHTON ELECTRONICS

KK Instruction List

 
Bank Register Load Instructions
Mnemonic
Operation Address Mode Op-Code
(hex)
Bytes
/Cycles
Substituted
op-code
Notes
LDK1 Load K1 Immediate 42 2 / 2 -  
  Zero-page,X 54 2 / 4 -  
  Absolute DC 3 / 4 -  
LDK2
Load K2 Immediate C2 2 / 2 -  
  Zero-page 44 2 / 3 -  
  Zero-page,X D4 2 / 4 -  
  Absolute 0B 3 / 4 DC  
LDK3 Load K3 Immediate E2 2 / 2 -  
  Zero-page,X F4 2 / 4 -  
  Absolute FC 3 / 4 -  
Prefix Instructions
Mnemonic Operation Address Mode Op-Code
(hex)
Bytes
/Cycles
Substituted
op-code
Notes
K1_ K1 prefix Implied 83 1 / 1 03  
K2_ K2 prefix Implied C3 1 / 1 03  
K3_ K3 prefix Implied 43 1 / 1 03  
"2 in1" Instructions (standard op with implicit prefix)
Mnemonic Operation Address Mode Op-Code
(hex)
Bytes
/Cycles
Substituted
op-code
Notes
LDA_K2 LDA using K2 (X,ind) F3 2 / 6 A1  
  (ind),Y E3 2 / 5 B1  
  Absolute D3 3 / 4 AD  
STA_K1 STA using K1 (X,ind) B3 2 / 6 81  
  (ind),Y A3 2 / 6 91  
  Absolute 93 3 / 4 8D  
Jump and Return Instructions
Mnemonic Operation Address Mode Op-Code
(hex)
Bytes
/Cycles
Substituted
op-code
Notes
JMP_K3 JMP using K3 Absolute 13 3 / 3 4C 1
JSR_K3 JSR using K3 Absolute 23 3 / 6 20 1
RTS_K3 RTS using K3 Stack EB 1 / 6 60 1
RTI_K3 RTI using K3 Stack FB 1 / 6 40 2
Push and Pull Instructions
Mnemonic Operation Address Mode Op-Code
(hex)
Bytes
/Cycles
Substituted
op-code
Notes
PHK0 Push K0 Stack 4B 1 / 3 08  
PHK1 Push K1 Stack 6B 1 / 3 08  
PHK2 Push K2 Stack 7B 1 / 3 08  
PHK3 Push K3 Stack 5B 1 / 3 08  
PLYK1 Pull Y, copying the value to K1 Stack 63 1 / 4 7A 3
PLYK2 Pull Y, copying the value to K2 Stack 73 1 / 4 7A 3
PLYK3 Pull Y, copying the value to K3 Stack 53 1 / 4 7A 3
PLYIPL
Pull Y, copying value to IP lowbyte Stack 1B 1 / 4 7A 3
PLYIPH Pull Y, copying value to IP highbyte Stack 2B 1 / 4 7A 3
Miscellaneous Instructions
Mnemonic Operation Address Mode Op-Code
(hex)
Bytes
/Cycles
Substituted
op-code
Notes
NEXT
"Next." Jump (( IP )) and
post-increment IP by 2
(( IP++ )) 3B 1 / 9 4C 5
LDAW
LDA and copy pointer to W (X,ind) CB 2 / 6 A1 8
STAW
STA and copy pointer to W (X,ind) DB 2 / 6 81 8
TSB_K1 TSB using K1 Absolute 8B 3 / 6 0C  
    ( IP ) AB 3 / 6 0C 4
TRB_K1 TRB using K1 Absolute 9B 3 / 6 1C  
    ( IP ) BB 3 / 6 1C 4
SCAN_K3
Far Scan using K3. (Reads bytes
for video horizontal scan line.)
Absolute 33 3 / * 20 6
NOP1
One-cycle NOP Implied 03 2 / 2 03 9
K0<>K3 Exchange K0 and K3 Implied 5C 3 / 8 - 10
SINC
Single increment of IP Implied 02 2 / 2 - 7
DINC
Double increment of IP Implied 22 2 / 2 - 7

Note 1: K0 is exchanged with K3.
Note 2: K3_RTI is only useful as a form of jump, for a debugger perhaps. The KK typically did not use hardware interrupts because certain KK instructions can crash if interrupted. Circuitry to remedy this remains incomplete.
Note 3: KK pull instructions send PLY to the CPU. Pull instructions cannot be created using NOPs due to the need to increment SP. The Y in the mnemonics for KK pull instructions reminds the programmer of this compromise solution.
Note 4: I think I intended these for manipulation of pixel bit-maps, with IP providing accelerated addressing through the array. I don't recall whether the capability ever got used.
Note 5: NEXT is discussed on this page
Note 6: The K3_SCAN instruction is discussed here.
Note 7: SINC and DINC are discussed here.
Note 8: these instructions are used to provide X-Indirect-Y Addressing, explained here.
Note 9: 1CYNOP (1-cycle NOP) is intended for software timing loops
Note 10: K0<>K3 is used during initialization, before the 16MB map is enabled, as a means to load K0. Otherwise it is suicidal to load K0 but not the PC.

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