The Diablo Proprietary CPU

Laughton Electronics

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Data Paths in the Diablo CPU.
Click for CPU schematic


This page describes part of the Diablo 1345 Daisy-wheel printer. The digital "brain" in control of the 1345 is not a microprocessor but a proprietary 8-bit engine built out 3 PROM's and a few dozen TTL chips.

This elemental computer is a study in contrasts. There are lots of registers (32), but there's no memory as such; registers are the only storage. The instruction set is desperately limited (i.e., only ten instructions); however, the fact that all instructions are single-cycle enables the device to perform adequately.

Indeed, this processor and its remarkable software routinely manage motion in all four motors (2 servos & 2 steppers) simultaneously. More amazing yet is that this real-time multitasking is accomplished on a processor with no subroutine capability, no interrupt capability, nor even a Real Time Clock.

In the photos of the CPU board you'll notice some wiring mod's. These allow the board to run with 2732A EPROM's instead of the original 82S115 TTL PROM's. I chose 2732A's because they match the 24-pin package of the original chips. The pin assignments differ considerably, but the rewiring has been minimized by swapping certain address lines with others, and likewise shuffling some of the data lines. (Needless to say, the scrambled wiring is functional only if the file written to the EPROM gets pre-scrambled in a complementary fashion.)

Besides being easier to develop code with, the EPROM's also have greater capacity than the TTL parts (4096 bytes vs 512). The wire mod's extend the addressable program space from 512 to 2048 bytes; the other 2K of the extra capacity is unused.

Architecture and Instruction Set

Referring to the Data Path diagram, notice the loop at the top, from the Program Counter (PC) to the Program PROM's to Operand Register A and back to the PC. This loop supports sequential program execution and conditional branching, as follows: at the end of an instruction cycle the PC will usually increment, causing the next sequential instruction to execute. But the JNC is a conditional jump instruction. It will either increment the PC or cause it to load instead, effecting a jump according to a bit field taken out of the 16-bit-wide instruction at the PROM outputs. The jump occurs only if the Carry/Zero Flag (not shown) is clear. (Instructions other than JNC use the bit field for alternative functions: it can supply the instruction with an 8-bit constant or it can address a register or an I/O port.)

The rest of the Data Path diagram centers around the Register File. Buses run from the Register File to the Operand A and B registers to the Adder and back. Each instruction cycle includes time for three accesses to the register file: a read of one location, and a read and a write of a second location. The write is optional, and sometimes one or both of the reads produce results that just get discarded. In all cases Operand A and B registers buffer the intermediate results.

A typical instruction reads one register, then another, and writes the sum back to the second location. This basic pattern has some useful variations. As already noted, Operand A may be "immediate" data, a program constant. Adding zero (via mux B) is how a move (copy) is accomplished from one register-file location to another. And (besides the 8-Bit Adder) Operand Registers A and B also feed some comparator gates (not shown) for bit testing.

Several instructions only use one of the register-file accesses. For example, a word in the file may be sent to an output port, or replaced with data from an input port. The XLAT instruction does a translate ("lookup") operation via tables stored in the Table PROM. (Lookups are used in various ways; for example, to find the hammer intensity associated with any given petal of the print-wheel.)

Every instruction op-code uses three bits (I1, I2 and I3; see schematic) to select Operand A, select Operand B, and determine whether a write will occur to the register file. This yields eight basic instructions, one of which has three variants.


Servicing the Unserviceable
extra (main index)   — for registerheads only
copyright notice (Jeff Laughton)